PXR40RM Datasheet, PDF (1213/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.2.10.2 ETPUCxSCR - eTPU Channel x Status Control Register
ETPUCxSCR gathers the interrupt status bits of the channel, and also the Function Mode definition
(read-write). Bits CIS, CIOS and DTRS for each channel can be also accessed from ETPUCISR,
ETPUCIOSR and ETPUCDTRSR registers respectively (see Section 29.2.9, Global Channel Registers).
Host must write 1 to clear a status bit.
Channel_Register_Base + 0x4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CIS CIOS 0
0
0
0
0
0 DTRS DTR 0
0
0
0
0
0
OS
W
CIC CIOC
DTRC DTR
OC
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
IPS OPS OBE 0
0
0
0
0
0
0
0
0
0
0
FM
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-24. ETPUCxSCR Register
CIS — Channel Interrupt Status
1 = channel has a pending interrupt to the Host CPU.
0 = channel has no pending interrupt to the Host CPU.
CIC — Channel Interrupt Clear
1 = clear interrupt status bit.
0 = keep interrupt status bit unaltered.
These bits are mirrored in ETPUCISR - see Section 29.2.9.1, ETPUCISR - eTPU Channel Interrupt
Status Register). See also the eTPU Reference Manual for details.
CIOS — Channel Interrupt Overflow Status
1 = interrupt overflow asserted for this channel
0 = interrupt overflow negated for this channel
CIOC — Channel Interrupt Overflow Clear
1 = clear status bit.
0 = keep status bit unaltered.
These bits are mirrored in ETPUCIOSR - see Section 29.2.9.3, ETPUCIOSR - eTPU Channel Interrupt
Overflow Status Register). See also Section 29.3.2.2.2, Interrupt and Data Transfer Request Overflow.
DTRS — Data Transfer Request Status
1 = Channel has a pending data transfer request.
0 = Channel has no pending data transfer request.
DTRC — Data Transfer Request Clear
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-45