PXR40RM Datasheet, PDF (1147/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
DECFILT_x_MSR[DIVR] bit is cleared by writing a one to the DECFILT_x_MSR[DIVRC] bit. Note
however, in enhanced debug mode, the set condition has higher priority than the clear. This means that if
the set condition occurs at the same time the CPU writes the clear bit (DECFILT_x_MSR[IBIC] to clear
the interrupt, the interrupt remains asserted.
28.3.12.1.3 Input Buffer DMA Request
This DMA request is enabled by setting the IO_SEL field and the DSEL bit in the DECFILT_x_MCR
register. When CPU/DMA is selected as the input data source, the input buffer DMA request is asserted
when the input buffer is available to receive a conversion sample (it is not holding a word of data). This
DMA request is cleared when an input data word is written to the input buffer. Therefore, the DMA request
is always cleared before it is asserted again. This DMA request can also be cleared by a soft reset.
28.3.12.1.4 Input Buffer Enhanced Debug Monitor DMA Request
When an eQADC is the input data source, DMA is enabled, and enhanced debug is enabled, the input
sample data can be read by DMA when this DMA request is asserted. The request is asserted when a new
word of sample data is written into the input buffer to be processed. As this filter register is overwritten by
the next word of sample data, a DMA read overrun event can occur (the DECFILT_x_MSR[DIVR] bit is
asserted) if the DMA request is not cleared before, or at the same time as, a new sample arrives to set the
DMA request. The DECFILT_x_MSR[DIVR] bit is cleared by writing one to the
DECFILT_x_MSR[DIVRC] bit or by soft reset.
28.3.12.2 Output Buffer Interrupt and DMA Requests
28.3.12.2.1 Output Buffer Interrupt
This interrupt is enabled by setting the DECFILT_x_MCR[OBIE] bit, and is asserted when the output
buffer is updated, CPU is selected for the output destination, and DMA is disabled. The
DECFILT_x_MSR[OBIF] flag bit is set when the interrupt request is asserted.
The output buffer interrupt request can also be asserted when DECFILT_x_MCR[SDIE] = 1, and an
integrator result is ready to be read. This condition is indicated when the DECFILT_x_MXSR[SDF] bit is
set. Note that both the filter output and integrator output share the same interrupt source.
This interrupt request is cleared by writing a 1 to the bit DECFILT_x_MSR[OBIC] and/or the
DECFILT_x_MXSR[SDFC] bits, or by a soft reset command.
28.3.12.2.2 Output Buffer DMA Request
When the CPU is selected as the output destination, and DMA is enabled, the output buffer can be read
using DMA. The output buffer DMA request is asserted when the output buffer receives a new result from
the filter. This DMA request is cleared when the output buffer is read by the processor, or a soft reset
occurs.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-33