PXR40RM Datasheet, PDF (1096/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
27.7.9.1.2 RSD Overview
Input
Voltage
x2
+
VRH _-
+
VRL _-
Residue Voltage
Sum
-VREF,0,VREF
Logic
Control
Digital
Signal
RSD
Adder
Figure 27-70. RSD Stage Block Diagram
On each pass through the RSD stage, the input signal will be multiplied by exactly two, and summed with
either -VREF, 0, or VREF, depending on the Logic Control. The Logic Control will determine -VREF, 0,
or VREF depending on the two comparator inputs. As the Logic Control sets the summing operation, it
also sends a digital value to the RSD adder. Each time an analog signal passes through the RSD
single-stage, a digital value is collected by the RSD adder. At the end of an entire AD conversion cycle,
the RSD adder uses these collected values to calculate the 12-bit/10-bit/8-bit digital output.
Figure 27-71 shows the transfer function for the RSD stage. Note how the digital value (a, b) is dependent
on the two comparator inputs.
27-114
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor