PXR40RM Datasheet, PDF (1384/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
NOTE
The output port mode control bit (OPC) and MCKO clock divide ratio bits
(MCK_DIV) must only be modified during system reset or debug mode to
insure correct output port and output clock functionality. It is also
recommended that all other bits of the DC1 only be modified in one of these
two modes.
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EWC
W
000000000000000000000000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-44. Development Control Register 2 (DC2)
Table 31-38. DC2 Field Description
Field
Description
0–7
EWC¹
EVTO Watchpoint Configuration
00000000 = No watchpoints trigger EVTO
1XXXXXXX = Invalid value
X1XXXXXX = Invalid value
XX1XXXXX = Invalid value
XXX1XXXX = Invalid value
XXXX1XXX = Internal watchpoint #1 triggers EVTO
XXXXX1XX = Internal watchpoint #2 triggers EVTO
XXXXXX1X = Invalid value
XXXXXXX1 = Invalid value
8–31
Reserved, read as 0.
1 _{The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint occurrence for the EWC bits to have any}
effect.
31-68
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor