PXR40RM Datasheet, PDF (838/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
24.3.4.9 Interrupt Masks 2 Register (FLEXCAN_x_IMASK2)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (i.e. when the corresponding FLEXCAN_x_IFLAG2
bit is set).
Base + 0x0024
R
W
RESET:
0
BUF
63M
0
1
BUF
62M
0
2
BUF
61M
0
3
BUF
60M
0
4
BUF
59M
0
5
BUF
58M
0
6
BUF
57M
0
7
BUF
56M
0
8
BUF
55M
0
9
BUF
54M
0
10
BUF
53M
0
11
BUF
52M
0
12
BUF
51M
0
13
BUF
50M
0
14
BUF
49M
0
15
BUF
48M
0
R
W
RESET:
16
BUF
47M
0
17
BUF
46M
0
18
BUF
45M
0
19
BUF
44M
0
20
BUF
43M
0
21
BUF
42M
0
22
BUF
41M
0
23
BUF
40M
0
24
BUF
39M
0
25
BUF
38M
0
26
BUF
37M
0
27
BUF
36M
0
28
BUF
35M
0
29
BUF
34M
0
30
BUF
33M
0
31
BUF
32M
0
Figure 24-11. Interrupt Masks 2 Register (FLEXCAN_x_IMASK2)
Table 24-13. FLEXCAN_x_IMASK2 Field Descriptions
Field
Description
0–31 Buffer MB_i Mask
BUF63M Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63) Interrupt.
–BUF32 0 The corresponding buffer Interrupt is disabled
M 1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the FLEXCAN_x_IMASK2 Register can assert or negate an interrupt request, if the
corresponding FLEXCAN_x_IFLAG2 bit is set.
24.3.4.10 Interrupt Masks 1 Register (FLEXCAN_x_IMASK1)
This register allows to enable or disable any number of a range of 32 Message Buffer Interrupts. It contains
one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after
a successful transmission or reception (i.e., when the corresponding FLEXCAN_x_IFLAG1 bit is set).
Base + 0x0028
R
W
RESET:
0
BUF
31M
0
1
BUF
30M
0
2
BUF
29M
0
3
BUF
28M
0
4
BUF
27M
0
5
BUF
26M
0
6
BUF
25M
0
7
BUF
24M
0
8
BUF
23M
0
9
BUF
22M
0
10
BUF
21M
0
11
BUF
20M
0
12
BUF
19M
0
13
BUF
18M
0
14
BUF
17M
0
15
BUF
16M
0
R
W
RESET:
16
BUF
15M
0
17
BUF
14M
0
18
BUF
13M
0
19
BUF
12M
0
20
BUF
11M
0
21
BUF
10M
0
22
BUF
9M
0
23
BUF
8M
0
24
BUF
7M
0
25
BUF
6M
0
26
BUF
5M
0
27
BUF
4M
0
28
BUF
3M
0
29
BUF
2M
0
30
BUF
1M
0
31
BUF
0M
0
Figure 24-12. Interrupt Masks 1 Register (FLEXCAN_x_IMASK1)
24-28
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor