PXR40RM Datasheet, PDF (1235/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Delays introduced by synchronizer, filter and edge detection logic are explained in the eTPU Reference
Manual.
Table 29-19. Pulse Widths and Delays
Filter Control
(FPSCK)
FCSS = 0 FCSS = 1
Filter Clock
Period¹
Min. Width Guaranteed Detected / Max. Width filtered
(Min. Filter Delay / Max. Filter Delay)¹
Two-Sample or Continuous
Mode
Three-Sample or Integrator²
Mode
not avail.
000
1
2 / 1 (2 / 3)
3 / 2 (3 / 4)
000
001
2
4 / 2 (3 / 3)
6 / 4 (5 / 5)
001
010
4
8 / 4 (5 / 7)
12 / 8 (9 / 11)
010
011
8
16 / 8 (9 / 15)
24 / 16 (17 / 23)
011
100
16
32 / 16 (17 / 31)
48 / 32 (33 / 47)
100
101
32
64 / 32 (33 / 63)
96 / 64 (65 / 95)
101
110
64
128 / 64 (65 / 127)
192 / 128 (129 / 191)
110
111
128
256 / 128 (129 / 255)
384 / 256 (257 / 383)
111
not avail.
256
512 / 256 (257 / 511)
768 / 512 (513 / 767)
1 _{This table shows pulse widths and delays in number of periods of the eTPU clock.}
2 _{Integrator mode is available for TCRCLK filtering only, see Section 29.3.5.5, TCRCLK Digital Filter.}
NOTE
If the ETPUTBCR field TCRCF selects the filter clock of the channels (see
Section 29.2.6.1, ETPUTBCR - eTPU Time Base Configuration Register),
the TCRCLK filter will be clocked as if FCSS=0, always dividing eTPU
clock /2 using FPSCK, regardless if FCSS is 0 or 1.
29.3.5 Time Bases
Each eTPU engine has two Time Counter Registers, TCR1 and TCR2. They provide 24-bit time bases,
shared by all 32 channels. TCR1 can also work at full-speed eTPU clock, when ETPUTBCR[TCR1CS]=1
Both TCR1 and TCR2 values can be imported from or exported to the STAC bus. For information on
STAC bus protocol and definition of STAC modules refer to IPI STAC and Section 29.3.5.3, STAC
Interface.
The TCR2 counters between the two Engines are out of phase by 1 eTPU clock, even when Time Bases
are shared between them through STAC.
29.3.5.1 Timer Count Register 1 - TCR1
TCR1 can be used in the following modes:
• Internally Clocked Mode
• Externally Clocked Mode
• STAC Bus Client Mode
The host program can read TCR1 time base through the ETPUTB1R (see Section 29.2.6.2, ETPUTB1R -
eTPU Time Base 1 (TCR1) Visibility Register).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-67