PXR40RM Datasheet, PDF (355/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

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Flash bus
interface
unit
(FBIU)
Flash Memory Array and Control
Flash_A Array
Flash memory
interface
(MI)
Control/status
registers
Flash core
Flash_B Array
Flash memory
interface
(MI)
Control/status
registers
Flash core
Figure 12-2. Flash Memory Module Block Diagram
12.1.2 Features
The flash memory module has these major features:
• Support for a 64-bit data bus for instruction fetch.
• Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and
doubleword reads are supported. Only aligned word and doubleword writes are supported.
• Configurable read buffering and line prefetch support. Two sets of buffers (one for 128-bit accesses
and one for 256-bit accesses) and a prefetch controller are used to support single-cycle read
responses for hits in the buffers.
• Hardware and software configurable read and write access protections on a per-master basis.
• Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses
to proceed in parallel.
• Configurable access timing allowing use in a wide range of system frequencies.
• Multiple-mapping support and mapping-based block access timing (0-31 additional cycles)
allowing use for emulation of other memory types.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12-3