PXR40RM Datasheet, PDF (368/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
12.2.2.4 Secondary Low/Mid Address Space Block Locking Register
(FLASH_x_SLMLR)
The Secondary Low/Mid Address Block Locking Register (FLASH_x_SLMLR) provides an alternative
means to protect blocks from being modified. This has the effect of creating a “tiered” locking scheme to
enable different flash users to provide different default locking on blocks. These bits, along with bits in the
LLOCK (FLASH_x_LMLR), determine if the block is locked from program or erase. An “OR” of
FLASH_x_LMLR and FLASH_x_SLMLR determine the final lock status.
NOTE
A reset value of 1* in Figure 12-6 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The following field and bit descriptions fully define the FLASH_x_SLMLR register (Figure 12-6).
Offset 0x000C / 0x400C
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SLE 0 0 0 0 0 0 0 0 0 0 _SS 0 0 _SM 0 0 0 0 0 0
W
LOCK
LOCK
SLLOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 1* 0 0 1* 1* 0 0 0 0 0 0 1* 1* 1* 1* 1* 1* 1* 1* 1* 1*
Figure 12-6. FLASH_x_SLMLR Register
NOTE
Writing the password 0xC3C3_3333 to this register does not modify the
SSLOCK, SMLOCK, or SLLOCK fields. Only the SLE bit changes.
FLASH_x_SLMLR register functions, as shown in Table 12-8.
Table 12-8. FLASH_x_SLMLR Field Descriptions
Field
0
SLE
1–10
11
SSLOCK
12–13
Description
Secondary Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SSLOCK,
SMLOCK, and SLLOCK) to be set or cleared by register writes. This bit is a status bit only, and may
not be written or cleared, and the reset value is 0. The method to set this bit is to provide a password,
and if the password matches, the SLE bit is set to reflect the status of enabled, and is enabled until
a reset operation occurs. For SLE, the password 0xC3C3_3333 must be written to the
FLASH_x_SLMLR register
0 Secondary Low/Mid Address Locks are disabled, and can not be modified.
1 Secondary Low/Mid Address Locks are enabled to be written.
Reserved
Secondary Shadow Lock. This bit is an alternative method that may be used to lock the shadow block
from programs and erases. SSLOCK has the same description as SLOCK in the FLASH_x_LMLR
register (see Figure 12-4). SSLOCK is not writable unless SLE is high.
Reserved
12-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor