PXR40RM Datasheet, PDF (519/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Periodic Interrupt Timer (PIT_RTI)
Offset channel_base + 0x0C
RTI base = 0x0F0
CH0 base = 0x100
CH1 base = 0x110
CH2 base = 0x120
CH3 base = 0x130
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0000000000000
Figure 20-6. Timer Flag Register (PIT_RTI_TFLG, PIT_CHn_TFLG)
30
31
0
TIF
00
Table 20-6. PIT_RTI_TFLG, PIT_CHn_TFLG Field Descriptions
Field
0–30
31
TIF
Description
Reserved
Time Interrupt Flag. TIF is set to 1 at the end of the timer period.This flag can be cleared only by
writing it with a 1. Writing a 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0 Time-out has not yet occurred
1 Time-out has occurred
20.4 Functional Description
20.4.1 General
This section gives detailed information on the internal operation of the module. Each timer can be used to
generate a unique interrupt vector.
20.4.1.1 Timers
Once enabled, the timers can be configured to generate interrupts at periodic intervals. The timer loads its
start value, as specified in the LDVAL register, then counts down until the count reaches 0. Then the value
in the LDVAL register is loaded again and the process repeats. Each time the timer reaches 0, an interrupt
is generated if enabled, and the interrupt flag is set.
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers). A new interrupt
can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
20-7