PXR40RM Datasheet, PDF (1218/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.3.2.2.2 Interrupt and Data Transfer Request Overflow
If a Channel Interrupt was issued, its status bit is still set, and microcode issues another Channel Interrupt,
the Interrupt Overflow status bit is set for that channel. Interrupt Overflow status can be checked by the
Host in Channel Status register ETPUCxSCR bit CIOS (Section 29.2.10.2, ETPUCxSCR - eTPU Channel
x Status Control Register), mirrored in register ETPUCIOSR (Section 29.2.9.3, ETPUCIOSR - eTPU
Channel Interrupt Overflow Status Register). Interrupt Overflow status is not cleared automatically when
Interrupt Status is cleared. The same mechanism and respective registers (ETPUCDTROSR) are available
for Data Transfer Requests.
If interrupt is set and cleared at the same time, set prevails and overflow is not altered (keeps the same state
as it was before, asserted or not).
Global Exception has no overflow status.
29.3.2.3 Parameter Access
29.3.2.3.1 Parameter Access Widths
From the Host side the SDM address space is mapped in bytes, and each 32-bit parameter occupies 4
contiguous, aligned bytes. The Host can read/write the SDM by 8-, 16-, or 32-bit accesses in aligned
addresses.
In 32-bit access, Host can access all 32 bits or only the lower 24 bits with an automatic sign extension (see
Section 29.3.2.3.4, Parameter Sign Extension Area).
29.3.2.3.2 Parameter Addresses and Endianness
To access parameter number xxx, eTPU Microengine(s) would select address xxx. The Host would add
(xxx*4) to the SDM base address to access the same parameter. For example, parameter 0x101 is seen by
the Host in (SDM base address +0x404). An example of SDM memory map is shown in Figure 29-26. The
Host can access the SDM with a 32-bit-wide bus cycle to a four-byte aligned address, 16-bit-wide bus
cycle to a two-byte aligned address, or 8-bit wide bus cycle to any byte address.
The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU.
29.3.2.3.3 Parameter Concurrency
Host accesses to parameters may occur in parallel with eTPU Microengine accesses. Readings taken from
a group of parameters while they are being simultaneously updated may lack coherency. eTPU provides
mechanisms to ensure parameter coherency in accesses from both Host side and Microengine side,
including the use of a coherent dual-parameter transfer mechanism, described in detail on Section 29.3.4,
Parameter Sharing and Coherency.
29.3.2.3.4 Parameter Sign Extension Area
The SDM address space to the Host is mirrored in a Parameter Sign Extension - PSE - area (see
Section 29.2.4, Memory Map). Accesses from the Host to the PSE area differ from accesses to the standard
SDM address space as follows:
29-50
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor