PXR40RM Datasheet, PDF (128/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Resets
assertion of the internal reset signal. Once the JTAG reset request is negated and the FMPLL Loss of Lock
reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer
to Section 4.3.2, RSTOUT). Once the clock count finishes the reset configuration pins are sampled, and
the associated bits/fields are updated in the SIU_RSR. The reset status bits in the SIU_RSR are unaffected.
Refer to Chapter 32, IEEE 1149.1 Test Access Port Controller (JTAGC), for more information.
4.5.7 Software System Reset
A Software System Reset is caused by a write to the SSR bit in the System Reset Control Register
(SIU_SRCR), Section 7.3.1.3, System Reset Control Register (SIU_SRCR). A write of one to the SSR bit
causes an internal reset of the MCU. The internal reset signal and RSTOUT pin are asserted. The value on
the WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), as is the
PLLREF value. The SSR bit is automatically cleared and once the FMPLL Loss of Lock reset request
signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT). Once the clock count finishes the reset configuration pins are sampled. The reset
controller then waits 4 clock cycles before negating RSTOUT, and the associated bits/fields are updated
in the SIU_RSR. In addition, the SSRS bit is set, and all other reset status bits in the SIU_RSR are cleared.
4.5.8 Software External Reset
A write of one to the SER bit in the SIU_SRCR causes the external RSTOUT pin to be asserted for a
predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). The SER bit automatically clears
after the clock counting expires. A Software External Reset does not cause a reset of the MCU, the BAM
program is not executed, the reset configuration pins are not sampled. The SERF bit in the SIU_RSR is
set, but no other status bits are affected. The SERF bit in the SIU_RSR is not automatically cleared after
the 6000 clock cycles expire, and remains set until cleared by software or another reset besides the
Software External Reset occurs.
For a Software External Reset, the e200z7 core will continue to execute instructions, timers that are
enabled will continue to operate, and interrupt requests will continue to be processed. It is the
responsibility of the application to ensure devices connected to RSTOUT are not accessed during a
Software External Reset, and to determine how to manage MCU resources when using the Software
External Reset.
4.6 Reset Registers in the SIU
The System Integration Unit (SIU) on this device includes two registers, SIU_RSR and SIU_SRCR, that
affect the reset behavior of this device. See Chapter 7, System Integration Unit (SIU),for descriptions of
these registers.
PXR40 Microcontroller Reference Manual, Rev. 1
4-8
Freescale Semiconductor