PXR40RM Datasheet, PDF (1079/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
The ADC conversion speed (in K samples per second - Ksps) is calculated by the following formula. The
number of sampling cycles is determined by the LST bits in the command message — see Conversion
Command Format for the Standard Configuration — and it can take one of the following values: 2, 8, 64,
or 128 ADC clock cycles. The number of AD conversion cycles is 13 for differential conversions and 14
for single-ended conversions (12 bits resolution and unitary input gain). The maximum conversion speed
is achieved when the ADC Clock frequency is set to its maximum, the number of sampling cycles set to
its minimum (2 cycles), and the resolution is also set to the minimum (8 bits) with input unitary gain.
ADCConversionSpeed = _---_N----_u----_m----_b----_e---_r--_O-----_f--_S---_a----_m-----_p---_l-^A-_i--_n-^D--_g---^C-_C---^C-_y---_c-^l--^ol--_e-^c--_s-^k---+^F----^r-_N--^e--_u-^q---_mu----^eb---ⁿ-_e--^c-_r--^yO---^--_f-^M-_A----^HD-----^zC--^--_o---_n----_v---_e---_r--_s---_i--_o----_n---_C----_y---_c---_l--_e---_s---_-
Table 27-40 shows an example of how the ADC0/1_CLK_PS can be set when using a 120 MHz platform
clock and the corresponding conversion speeds for all possible ADC clock frequencies. The table also
shows that according to the platform clock frequency, certain clock divide factors are invalid (2, 4, 6, 8
clock divide factors in the example) since their use would result in a ADC clock frequency higher than the
maximum one supported by the ADC. In this example, the maximum ADC clock frequency is 15 MHz (12
bits resolution conversions with unitary input gain).
Table 27-40. ADC Clock Configuration Example (Platform Clock Frequency=120 MHz)
ADC0/1_CLK_PS[0:4]
0b00000
0b00001
0b00010
0b00011
0b00100
0b00101
0b00110
0b00111
0b01000
0b01001
0b01010
0b01011
0b01100
0b01101
0b01110
0b01111
0b10000
0b10001
0b10010
0b10011
0b10100
0b10101
Platform Clock
Divide Factor
ADC Clock
(Platform Clock
= 120 MHz)
Differential
Conversion Speed
with Default Sampling
Time (2 cycles)
Single-Ended
Conversion Speed
with Default Sampling
Time (2 cycles)
2
N/A
N/A
N/A
4
N/A
6
N/A
8
15.0 MHz
10
12.0 MHz
12
10.0 MHz
14
8.57 MHz
16
7.5 MHz
18
6.67 MHz
20
6.0 MHz
N/A
N/A
1.0 Msps
800 Ksps
667 Ksps
571 Ksps
500 Ksps
444 Ksps
400 Ksps
N/A
N/A
938 Ksps
750 Ksps
625 Ksps
536 Ksps
469 Ksps
417 Ksps
375 Ksps
22
5.45 MHz
24
5.0 MHz
26
4.62 MHz
28
4.29 MHz
30
4.0 MHz
32
3.75 MHz
34
3.53 MHz
36
3.33 MHz
38
3.16 MHz
364 Ksps
333 Ksps
308 Ksps
286 Ksps
267 Ksps
250 Ksps
235 Ksps
222 Ksps
211 Ksps
341 Ksps
313 Ksps
288 Ksps
268 Ksps
250 Ksps
234 Ksps
221 Ksps
208 Ksps
198 Ksps
40
3.0 MHz
42
2.86 MHz
44
2.73 MHz
200 Ksps
190 Ksps
182 Ksps
188 Ksps
179 Ksps
170 Ksps
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-97