PXR40RM Datasheet, PDF (443/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

AMBA Crossbar Switch (XBAR)
14.3.6.1 Fixed Priority Operation
When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the
XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the
selected priority register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new requesting
master’s priority level is higher than that of the master that currently has control over the slave port (if any).
The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has
control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port, the higher priority master is granted control at the termination of any currently pending
access, assuming the pending transfer is not part of a burst transfer.
A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted
control of the slave port. But if the new requesting master’s priority level is lower than that of the master
that currently has control of the slave port, the new requesting master is forced to wait until the master that
currently has control of the slave port is finished accessing the current slave port.
14.3.6.2 Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master port
number. This relative priority is compared to the port number of the last master to perform a transfer on
the slave bus. The highest priority requesting master becomes the owner of the slave bus at the next transfer
boundary (accounting for fixed-length burst transfers). Priority is based on how far ahead the port number
of the requesting master is to the port number of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line is granted access to the slave
port when the current transfer is completed, or possibly on the next clock cycle if the current master has
no pending access request.
As an example of arbitration in round-robin mode, assume the three masters have ID’s 0, 1, and 2. If the
last master of the slave port was master 1, and masters 0 and 2 make simultaneous requests, they are
serviced in the order 2 and then 0 assuming no further requests are made.
As another example, if master 1 is waiting on a response from a slow slave and has no further pending
access to that slave, no other masters are requesting, and master 0 then makes a request, master 0’s request
is granted on the next clock (assuming that master 1’s transfer is not a burst transfer), and the request
information for master 0 is driven to the slave as a pending access. If master 2 were to make a request after
master 0 has been granted access, but prior to master 0’s access being accepted by the slave, master 0
maintains the grant on the slave port, and master 2 is delayed until the next arbitration boundary, which
occurs after the transfer is complete. The round-robin pointer is reset to 0, so if master 1 has another request
that occurs before master 0’s transfer completes, master 1 is the granted the bus. This implies a worst case
latency of N transfers for a system with N masters.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
14-11