PXR40RM Datasheet, PDF (903/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

SoC
DSPI Master
SIN
SOUT
HT
PCS[x] SCK
DSPI Slave
SIN
SOUT
MTRIG
SS
HT
SCK
Deserial Serial Peripheral Interface (DSPI)
DSPI Slave
SIN
SOUT
MTRIG
SS
SCK
SS
SOUT
SCK
SIN
SPI Slave Device
Figure 25-23. Example of Serial Chaining of DSPIs
The SOUT of the DSPI Master is connected to the SIN of the first DSPI slave. The SOUT of the first DSPI
slave is connected to the SIN input of the second slave and so on. The SOUT of the last DSPI slave is
connected to the SIN of the external SPI slave. The SOUT of the external SPI slave is connected to the
SIN of the DSPI master.
The DSPI master controls and initiates all transfers, but the slave DSPIs use the trigger output signal
MTRIG to indicate to the DSPI master that a trigger condition has occurred. When a DSPI slave has a
change in data to be serialized it asserts the MTRIG signal to the DSPI master which initiates the transfer.
When a DSPI slave has its HT signal asserted it will assert its MTRIG signal thereby propagating trigger
signals from other DSPI slaves to the DSPI master.
The MTOCNT field in the DSPI_DSICR must be written with the total number of bits to be transferred.
The MTOCNT field must equal the sum of all FMSZ fields in the selected DSPI_CTAR registers for the
DSPI master and all DSPI slaves. For example if one 16-bit DSI frame is created by concatenating eight
bits from the DSPI master, and four bits from each of the DSPI slaves in Figure 25-23, the DSPI master’s
frame size must be set to eight in the FMSZ field, and the DSPI slaves’ frame size must be set to four. The
largest DSI frame supported by the MTOCNT field is 64 bits. Any number of DSPIs can be connected
together to concatenate DSI frames, as long as each DSPI transfers a minimum of 4 bits and a maximum
of 16 bits and the total size of the concatenated frame is less than or equal to 64 bits long.
25.4.5 Combined Serial Interface (CSI) Configuration
The CSI Configuration of the DSPI is used to support SPI and DSI functions on a frame by frame basis.
CSI Configuration allows interleaving of DSI data frames from the Parallel Input signals with SPI
commands and data from the TX FIFO. The data returned from the bus slave is either used to drive the
Parallel Output signals or it is stored in the RX FIFO. The CSI Configuration allows serialized data and
configuration or diagnostic data to be transferred to a slave device using only one serial link. The DSPI is
in CSI Configuration when the DCONF field in the DSPI_MCR is 0b10. Figure 25-24 shows an example
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-43