PXR40RM Datasheet, PDF (416/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
The IVOR fields are defined in Table 13-15.
Table 13-15. IVOR Register Fields
Field
Description
0–15
Reserved
16–27
Vector Offset
Vector Offset
This field is used to provide a quadword index from the base address provided by the IVPR to
locate an interrupt handler.
28–31 Reserved
13.9 Interrupt Definitions
13.9.1 Critical Input Interrupt (IVOR0)
A Critical Input exception is signalled to the processor by the assertion of the critical interrupt pin. When
the core detects the exception, if the exception is enabled by MSR_CE, the core takes the Critical Input
interrupt. The critical input is a level-sensitive signal expected to remain asserted until the core
acknowledges the interrupt. If critical input is negated early, recognition of the interrupt request is not
guaranteed. After the core begins execution of the critical interrupt handler, the system can safely negate
critical input.
Table below lists register settings when a Critical Input interrupt is taken.
Table 13-16. Critical Input Interrupt—Register Settings
Register
Setting Description
CSRR0
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
CSRR1 Set to the contents of the MSR at the time of the interrupt
MSR
UCLE 0
SPE 0
WE 0
CE 0
EE 0
PR 0
FP 0
ME —
FE0 0
DE —/0¹
FE1 0
IS 0
DS 0
PMM 0
RI —
ESR
Unchanged
MCSR
Unchanged
DEAR
Unchanged
Vector
IVPR_0:15 || IVOR0_16:27 || 4b0000 (autovectored)
IVPR_0:15 || p_voffset[0:11] || 4b0000 (non-autovectored)
1 _{DE is cleared when the Debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the}
Debug APU is enabled.
13-28
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor