PXR40RM Datasheet, PDF (894/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
The SPI and DSI configurations are valid in Slave Mode. In SPI Slave Mode the slave transfer attributes
are set in the DSPI_CTAR0. In DSI Slave Mode the slave transfer attributes are set in the DSPI_CTAR1.
In both SPI and DSI configurations the DSPI in Slave Mode transfers data MSB first. The LSBFE field of
the associated CTAR is ignored.
25.4.1.3 Module Disable Mode
The Module Disable Mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI can be stopped while in Module Disable Mode.The DSPI enters the Module Disable
Mode when the MDIS bit in DSPI_MCR is set or when a request for the DSPI to enter Doze Mode is
asserted by an external controller while the DOZE bit in the DSPI_MCR is asserted. Logic external to the
DSPI is needed to implement the Module Disable Mode. See Section 25.4.11, Power Saving Features, for
more details on the Module Disable Mode.
25.4.1.4 External Stop Mode
For devices with low-power modes, the DSPI supports the Stop Mode mechanism. The DSPI will not
acknowledge the request to enter External Stop Mode until it has reached a frame boundary. When the
DSPI has reached a frame boundary it will halt all operations and indicate that it is ready to have its clocks
shut off. The DSPI exits External Stop Mode and resumes normal operation once the clocks are turned on.
Serial communications or register accesses made while in External Stop Mode are ignored even if the
clocks have not been shut off yet. See Section 25.4.11, Power Saving Features, for more details on the
External Stop Mode.
25.4.1.5 Debug Mode
The Debug Mode is used for system development and debugging. If the device enters Debug Mode while
the FRZ bit in the DSPI_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the
device enters Debug Mode while the FRZ bit is negated, the DSPI behavior is unaffected and remains
dictated by the block-specific mode and configuration of the DSPI. The DSPI enters Debug Mode when a
debug request is asserted by an external controller. See Figure 25-19 for a state diagram.
25.4.2 Start and Stop of DSPI Transfers
The DSPI has two operating states; STOPPED and RUNNING. The states are independent of DSPI
configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are
initiated in Master Mode and no transfers are responded to in Slave Mode. The STOPPED state is also a
safe state for writing the various configuration registers of the DSPI without causing undetermined results.
The TXRXS bit in the DSPI_SR is negated in this state. In the RUNNING state serial transfers take place.
The TXRXS bit in the DSPI_SR is asserted in the RUNNING state. Figure 25-19 shows a state diagram
of the start and stop mechanism. The transitions are described in Table 25-26.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor