PXR40RM Datasheet, PDF (668/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
System Memory
Sync Frame Table Area
Message Buffer Data Area
Message Buffer Header Fields
Receive FIFO B
Message Buffer Header Fields
Receive FIFO A
Message Buffer Header Fields
Individual Message Buffers
Receive Shadow Buffers
Frame Header
Frame Header
Frame Header
Frame Header
Frame Header
Frame Header
Frame Header
Data Field Offset
Slot Status
Data Field Offset
Data Field Offset
Slot Status
Slot Status
Data Field Offset
Data Field Offset
Slot Status
Slot Status
Data Field Offset
Slot Status
Data Field Offset
Slot Status
SYMBADR[SMBA]
10 bytes
Figure 22-107. Example of FlexRay Memory Layout (MCR[FAM] = 0)
22.6.4.2 FlexRay Memory Layout (MCR[FAM] = 1)
Figure 22-108 shows an example layout for the FIFO address mode MCR[FAM]=1. The following set of
rules applies to the layout of the flexray memory:
• The flexray memory consists of two contiguous regions.
• The size of each region is maximum 64 Kbytes.
• Each region start at a 16 byte boundary.
22-84
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor