PXR40RM Datasheet, PDF (569/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine reads the entire TCD, including the primary
transfer control parameter shown in Table 21-22, for the selected channel into its internal address path
module. As the TCD is being read, the first transfer is initiated on the system bus unless a configuration
error is detected. Transfers from the source (as defined by the source address, EDMA_x_TCD.SADDR)
to the destination (as defined by the destination address, EDMA_x_TCD.DADDR) continue until the
specified number of bytes (EDMA_x_TCD.NBYTES) have been transferred. When the transfer is
complete, the DMA engine's local EDMA_x_TCD.SADDR, EDMA_x_TCD.DADDR, and
EDMA_x_TCD.CITER are written back to the main TCD memory and any minor loop channel linking is
performed, if enabled. If the major loop is exhausted, further post processing is executed; for example,
interrupts, major loop channel linking, and scatter-gather operations, if enabled.
Table 21-22. TCD Primary Control and Status Fields
TCD Field
Name
START
ACTIVE
DONE
D_REQ
BWC
E_SG
INT_HALF
INT_MAJ
Description
Control bit to start channel when using a software initiated DMA
service (Automatically cleared by hardware)
Status bit indicating the channel is currently in execution
Status bit indicating major loop completion (cleared by software
when using a software initiated DMA service)
Control bit to disable DMA request at end of major loop
completion when using a hardware-initiated DMA service
Control bits for throttling bandwidth control of a channel
Control bit to enable scatter-gather feature
Control bit to enable interrupt when major loop is half complete
Control bit to enable interrupt when major loop completes
Figure 21-28 shows how each DMA request initiates one minor loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (biter).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-45