PXR40RM Datasheet, PDF (1278/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
Table 30-10. EBI_CAL_OR0-3 Descriptions
Field
Description
0-16
AM
Address Mask
This field allows masking of any corresponding bits in the associated Base Register. Masking the address
independently allows external devices of different size address ranges to be used. Any clear bit masks the
corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the
address pins. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more
than one area of the address map. This field can be read or written at any time.
Note: An MCU may have some of the upper bits of the AM field tied to a fixed value internally in order to restrict the
address range of the EBI for that MCU. See the corresponding Note for the Base Register BA field for more
details.
17–23 Reserved
24–27
SCY
Cycle length in clocks
This field represents the number of wait states (external cycles) inserted after the address phase in the single
transfer case, or in the first beat of a burst, when the memory controller handles the external memory access. Values
range from 0 to 15. This is the main parameter for determining the length of the cycle. These bits are ignored when
SETA=1.
The total cycle length for the first beat (including the D_TS cycle) = (2+SCY) external clock cycles.
See Section Section 30.5.3.1, Example Wait State Calculation, for related application information.
28 Reserved
29–30
BSCY
Burst beats length in clocks
This field determines the number of wait states (external cycles) inserted in all burst beats except the first, when the
memory controller starts handling the external memory access and thus is using SCY[0:3] to determine the length
of the first beat. These bits are ignored when SETA=1.
The total memory access length for each beat is (1 + BSCY) external clock cycles.
The total cycle length (including the D_TS cycle) = (2+SCY) + (#beats¹-1) * (BSCY+1).
Value
00
01
10
11
Meaning
0-clock cycle wait states (1 clock per data beat)
1-clock cycle wait states (2 clocks per data beat)
2-clock cycle wait states (3 clocks per data beat)
3-clock cycle wait states (4 clocks per data beat)
31 Reserved
1 _{#beats is the number of beats (4,8,16) determined by BL and PS bits in Base Register.}
30.4 Functional Description
30.4.1 External Bus Interface Features
30.4.1.1 Address Bus (up to 22 available on pins)
. Valid transaction sizes are 8, 16 and 32 bits. Only 22 address lines are pinned out externally, but a full
32-bit decode is done internally to determine the target of the transaction and whether a chip select should
be asserted.
30-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor