PXR40RM Datasheet, PDF (920/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK
Master SOUT
PCS
Data Frame 1
Active Phase
Data Frame 2
Active Phase
0 LSB
Invalid
0 LSB
t_DT
Invalid
t_DT
t_DT = from 1 to (PDT * DT / f_periph) TSCK ^{Data Selection Bit}
Data Frame = 4 to 32 bits
Figure 25-40. TSB Data Frame Format
25.4.10 Interrupts/DMA Requests
The DSPI has four conditions that can only generate interrupt requests and two conditions that can
generate interrupt or DMA request. Table 25-35 lists the six conditions.
Table 25-35. Interrupt and DMA Request Conditions
Condition
End of Queue (EOQ)
TX FIFO Fill
Transfer Complete
TX FIFO Underflow
RX FIFO Drain
RX FIFO Overflow
Flag
EOQF
TFFF
TCF
TFUF
RFDF
RFOF
Interrupt
X
X
X
X
X
X
DMA
X
X
Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI
DMA/Interrupt Request Select and Enable Register (DSPI_RSER). The TX FIFO Fill Flag (TFFF) and
RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the TFFF_DIRS
and RFDF_DIRS bits in the DSPI_RSER.
25.4.10.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request
is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPI_RSER is asserted.
25.4.10.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
25-60
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor