PXR40RM Datasheet, PDF (936/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
26.3.2.1 Baud Rate Register (eSCI_BRR)
eSCI_BASE + 0x0000
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
R
W
SBR
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Figure 26-2. Baud Rate Register (eSCI_BRR)
This register provides the control value for the serial baud rate. The baud rate and clock generation is
specified in Section 26.4.3, Baud Rate and Clock Generation.
A byte write access to only the upper byte of this register (eSCI_BRR[0:7]) will not change the content of
the register, instead, the written byte is stored internally into a shadow register. A subsequent byte write
access to only the lower byte of this register (eSCI_BRR[8:15]) updates the lower byte and copies the
content of the shadow register into the upper byte.
A byte write access to only the lower byte of this register (eSCI_BRR[8:0]) without a preceding byte write
access to only the upper byte copies a value of all zero into the upper byte.
A word write access to this register updates both the lower and upper byte immediately and is the
recommended write access type for this register.
Table 26-5. eSCI_BRR Field Descriptions
Field
R
SBR
Description
Reserved. These bits are reserved. They are read as 0. Application must not write 1 to these bits.
Serial Baud Rate. This field provides the baud rate control value SBR.
26.3.2.2 Control Register 1 (eSCI_CR1)
eSCI_BASE + 0x0002
Write: Anytime
0
R
W
Reset 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RWU
R RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE
SBK
rwm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-3. Control Register 1 (eSCI_CR1)
This register provides bits to configure the functionality of the module, provides the interrupt enable bits
for the interrupt flags provided in Interrupt Flag and Status Register 1 (eSCI_IFSR1) and provides the
control bits for the transmitter and receiver.
26-8
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor