PXR40RM Datasheet, PDF (987/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
• Two independent on-chip RSD Cyclic ADCs
— 8, 10, and 12 bits AD Resolution
— Selectable common mode conversion range (0–5V; 0–2.5V; 0–1.25V)
— Differential conversions
— Differential channels include variable gain amplifier for improved dynamic range (x1; x2; x4)
— Differential channels include programmable pull-up and pull-down resistors for biasing and
sensor diagnostics (200k ohms; 100k ohms; 5k ohms)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
— Each conversion result can be marked with an imported timestamp from the eTPU, or an
independent timestamp
— Parallel interface to EQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
— Two REFBYPC pins for each EQADC module: REFBYPC25 and REFBYPC75
— Temperature sensor (available only to the primary ADC pair (eQADC_A’s ADC0 and ADC1)
— Ability to directly measure Vdd
• Automatic application of ADC calibration constants
• Parallel Side Interface allows eQADC_B to route conversion results without CPU intervention to
the Decimation Filter block for signal processing
• Priority Based CFIFOs
— Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority.
When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority
CFIFO is always served first.
— Immediate conversion command feature with conversion abort control
— Streaming mode operation of CFIFO0 to execute defined commands multiple times
— Supports software and several hardware trigger modes to arm a particular CFIFO
— Generates interrupt when command coherency is not achieved
• External (to the eQADC) Hardware Triggers
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
— Supports controls to bypass the trigger digital filters (refer to the SIU chapter)
• Two Triggers operation mode for queue0
— Additional internal trigger (not filtered) called Advance trigger that is used to enable the
external trigger of queue0 and to control the loop behavior of CFIFO0 (only available on
EQADC_B)
• Supports 4 to 8 external 8-to-1 muxes which can expand the input channel number from 40 to 96
27.3 Modes of Operation
This section describes the operation modes of the EQADC.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-5