PXR40RM Datasheet, PDF (1238/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
filter that provides best latency while maintaining proper noise filtering (see Section 29.2.6.1,
ETPUTBCR - eTPU Time Base Configuration Register field TCRCF[0:1] — TCRCLK Signal Filter
Control).
The TCR2 bus runs through all the local engine channels
The TCR2 value is readable to the host through the ETPUTB2R register (refer to Section 29.2.6.3,
ETPUTB2R - eTPU Time Base 2 (TCR2) Visibility Register). When the TCR2 bus value is imported from
the STAC bus (STAC client mode), TCR2 is not writable by the microcode, and read access from the
microcode or from the host reflect the imported TCR2 value.
29.3.5.2.1 TCR2 Clock Prescaling
Except in Angle Mode, any clock source selected by TCR2CTL is prescaled by a factor of 1 to 64, selected
by ETPUTBCR field TCR2P. For more information on prescaler configuration refer to Section 29.2.6.1,
ETPUTBCR - eTPU Time Base Configuration Register. The TCR2 Prescaler resets when etpu_gtbe_in is
negated. After reset, it starts counting up to TCR2P when etpu_gtbe_in is asserted. When TCR2
increments (etpu_gtbe_in=1), the prescaler starts a new count and the new TCR2P becomes effective.
The counter that divides the eTPU clock by 8 before the prescaler also resets when etpu_gtbe_in is
negated, or when TCR2 is written by microcode.
29.3.5.2.2 TCR2 Gated Mode
TCR2 Gated mode is selected in field TCR2CTL of register ETPUTBCR. In this mode the TCRCLK
signal enables or disables transfer of the eTPU clock divided by 8 to the TCR2 prescaler. By programming
the prescaler, TCR2 can run at rates from eTPU clock divided by eight down to eTPU clock divided by
512, in steps of eight eTPU clock divisions. For more information refer to Section 29.2.6.1, ETPUTBCR
- eTPU Time Base Configuration Register.
29.3.5.2.3 TCR2 Signal Transition Modes
These modes are selected when the TCR2CTL field in ETPUTBCR is set to rise, fall or “rise-and-fall”. In
these modes the TCRCLK signal is the TCR2 clock source, and its maximum transition rate depends on
the TCRCLK digital filter mode of operation. The TCRCLK digital filter can be programmed to use the
eTPU clock divided by two, or use the same filter clock of the channels, controlled by the TCRCF field in
ETPUTBCR. It contains an up-down counter which operates as a digital integrator, optimizing signal
latency in the selected mode and clock rate.
When eTPU clock divided by two is selected, the synchronizer and the digital filter are guaranteed to pass
pulses that are wider than four eTPU clocks (two filter clocks). Otherwise the TCRCLK is filtered with
the same filter clock as the channel input signals. For details on TCRCLK and channels digital filter
control refer to Section 29.2.6.1, ETPUTBCR - eTPU Time Base Configuration Register and
Section 29.3.4.4, Enhanced Digital Filter - EDF.
29.3.5.2.4 STAC Bus Client Mode
In this mode the TCR2 register is continuously updated from the STAC bus, and the clock selection and
prescaling logic becomes ineffective. It is not write accessible for the microcode, and when read, it reflects
29-70
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor