PXR40RM Datasheet, PDF (1401/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 32
IEEE 1149.1 Test Access Port Controller (JTAGC)
32.1 Introduction
The JTAG port of the device consists of four inputs and one output. These pins include JTAG compliance
select (JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock input
(TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and are shared with
the NDI through the test access port (TAP) interface.
32.1.1 Block Diagram
Figure 32-1 is a block diagram of the JTAG Controller (JTAGC).
JCOMP
Power-on
reset
TMS
TCK
Test access port (TAP)
controller
.
.
TDI
.
.
1-bit bypass register
32-bit device identification register
Boundary scan register
TDO
.
5-bit TAP instruction decoder
.
5-bit TAP instruction register
Figure 32-1. JTAG Controller Block Diagram
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
32-1