PXR40RM Datasheet, PDF (1172/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.1.1.1 eTPU Engine
Each eTPU Engine consists of two 24-bit time bases, 32 independent timer channels, a task scheduler, a
microengine, and a Host interface. In addition, each eTPU module has a 32-bit Shared Data Memory
(SDM) used for data storage and for passing information between the eTPU Engines and the Host CPU.
Figure 29-2 shows the block diagram for the eTPU Engine.
Red Line Red Line
INTERFACE
IPI
SkyBlue,
Green
Lines
HOST
INTERFACE
CONTROL
SCHEDULER
SERVICE REQUESTS
IPI
Indigo
Line
ENGINE
CONFIGURATION
TIME BASE
CONFIGURATION
IPI
DarkBlue
Line
CHANNEL
CONTROL
CONTROL
to NDEDI DEBUG
INTERFACE
CONTROL
and DATA
TCRCLK
PIN
TCR1
TCR2/
ANGLE COUNT
MICROENGINE
FETCH and
DECODE
EXECUTION
UNIT
MDU
CONTROL AND DATA
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
IPI
Purple
Line
(PINS)
CHANNEL 31
SHARED
PARAMETER
RAM
(SDM)
SHARED
CODE
MEMORY
(SCM)
Figure 29-2. eTPU Engine Block Diagram
Throughout this document, the term “eTPU” is sometimes used in place of “eTPU Engine”.
29.1.1.1.1 Time Bases
Two 24-bit counters TCR1 and TCR2 provide reference time bases for all match and input capture events.
Prescalers for both time bases are controlled by the Host CPU through bit fields in the eTPU Engine
29-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor