PXR40RM Datasheet, PDF (800/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EDPOL = 0
Cycle n
Write to A2
Cycle (n + 1)
Clock
Prescaler
Selected
Counter Bus
1
A1 Value 0x000004
A2 Value
B1 Value 0x000008
A1 Match
A1 Match Positive
Edge Detection
A1 Match Negative
Edge Detection
B1 Match
B1 Match Negative
Edge Detection
Output Pin
EDPOL = 0
4
0x000000
8
1
0x000000
8
Time
A1 Match Positive Edge Detection
A1 Match Negative Edge
Detection
A1 Match Negative Edge Detection
FLAG Set Event
FLAG Pin/Register
Figure 23-54. OPWMB Mode with 0% Duty Cycle
Figure 23-55 shows the operation of the OPWMB mode with the output disable signal asserted. The output
disable forces a transition in the output pin to the EDPOL bit value. After deassertion, the output disable
allows the output pin to transition at the following A1 or B1 match. The output disable does not modify
the flag bit behavior. There is a delay of one system clock between the assertion of the output disable signal
and the transition of the output pin to EDPOL.
23-60
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor