PXR40RM Datasheet, PDF (494/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Error Correction Status Module (ECSM)
Table 17-15. ECSM_REAT Field Descriptions
Field
0
WRITE
0 Read access.
1 Write access.
1–3
SIZE
000 8-bit access.
001 16-bit access.
010 32-bit access.
011 64-bit access.
1xx Reserved.
4–7
PROTECTION
Cache:
0xxx Non-cacheable.
1xxx Cacheable.
Buffer:
x0xx Non-bufferable.
x1xx Bufferable.
Mode:
xx0x User mode.
xx1x Supervisor mode.
Type:
xxx0 I-Fetch.
xxx1 Data.
Description
17.2.2.16 RAM ECC Data Register (ECSM_REDR)
The ECSM_REDR is a 64-bit register for capturing the data associated with the last properly enabled ECC
event in the RAM memory. Depending on the state of the ECC configuration register, an ECC event in the
RAM causes the address, attributes, and data associated with the access to be loaded into the
ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT, and ECSM_REDR registers and also the
appropriate flag (R1BC or RNCE) in the ECC status register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined. This register is read-only; any
attempted write is ignored. See Figure 17-15 and Table 17-16 for the RAM ECC data register definition.
Offset: ECSM_BASE_ADDR + 0x0068
Access: User read-only
0
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
REDR[0:15]
W
Reset U¹
U
U
U
U
U
U
U
U
UU U
U
U
U
U
16
R
W
Reset U
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REDR[16:31]
U
U
U
U
U
U
U
U
UU U
U
U
U
U
Figure 17-14. RAM ECC Data High (ECSM_REDRH) Register
1 _{U = undefined at reset}
17-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor