PXR40RM Datasheet, PDF (1064/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
When an EOQ or a Pause is encountered, the EQADC halts command transfers from the CFIFO and, if
enabled, the appropriate interrupt requests are generated. Another edge trigger event is required to resume
command transfers but no software involvement is required to rearm the CFIFO in order to detect such
event.
A trigger overrun happens when the CFIFO is already in TRIGGERED state and a new edge trigger event
is detected.
Continuous-Scan Level Trigger
When high or low level gated trigger mode is selected, the input level on the associated trigger signal
places the CFIFO in TRIGGERED state. When high-level gated trigger is selected, a high-level signal
opens the gate, and a low level closes the gate. The CFIFO commands start to be transferred when the
CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer. Although command
transfers will not stop upon detection of an asserted EOQ bit at the end of a command transfer, the EOQF
is asserted and, if enabled, an EOQ interrupt request is generated.
The EQADC stops transferring commands from a TRIGGERED CFIFO when CFIFO status changes from
TRIGGERED due to the detection of a closed gate. If a closed gate is detected while no command transfers
are taking place and the CFIFO status is TRIGGERED, the CFIFO status is immediately changed to
WAITING FOR TRIGGER and the PF flag is asserted.Command transfers will restart as the gate opens.
The Pause bit has no effect in continuous-scan level-trigger mode.
27.7.4.6.4 CFIFO Scan Trigger Mode Start/Stop Summary
Table 27-38 summarizes the start and stop conditions of command transfers from CFIFOs for all of the
single-scan and continuous-scan trigger modes.
Table 27-38. CFIFO Scan Trigger Mode - Command Transfer Start/Stop Summary
Trigger Mode
Requires
Asserted SSS
to Recognize
Trigger
Events?
Command Transfer
Start/Restart
Condition
Single Scan
Software
Single Scan
Edge
Single Scan
Level
Don’t Care Asserted SSS bit.
Yes
A corresponding edge
occurs.
Yes
Gate is opened.
Continuous
No
CFIFO starts
Scan Software
automatically after
being configured into
this mode.
Continuous
Scan Edge
No
A corresponding edge
occurs.
Stop on
asserted
EOQ
bit¹?
Stop on
asserted
Pause
bit²?
Other Command Transfer Stop
Condition^{3 4}
Yes
No None.
Yes
Yes None.
Yes
No EQADC also stops transfers
from the CFIFO when CFIFO
status changes from
TRIGGERED due to the
detection of a closed gate.⁵
No
No None.
Yes
Yes None.
27-82
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor