PXR40RM Datasheet, PDF (511/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Timer Module (STM)
19.3.2.4 STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
Offset 0x14+0x10*n
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-4. STM Channel Interrupt Register (STM_CIRn)
Table 19-5. STM_CIRn Field Descriptions
Field
Description
0–30
31
CIF
Reserved
Channel Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no
effect.
0 = No interrupt request.
1 = Interrupt request due to a match on the channel.
19.3.2.5 STM Channel Compare Register (STM_CMPn)
The STM channel compare register (STM_CMPn) holds the compare value for channel n.
Offset 0x18+0x10*n
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-5. STM Channel Compare Register (STM_CMPn)
Table 19-6. STM_CMPn Register Field Descriptions
Field
Description
0–31 Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the
CMP STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
19-5