PXR40RM Datasheet, PDF (409/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
13.5.1 Exception Syndrome Register
The Exception Syndrome Register (ESR) provides a syndrome to differentiate between exceptions that can
generate the same interrupt type.
0
0
0
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 62; Read/Write; Reset - 0x0
Figure 13-13. Exception Syndrome Register (ESR)
The ESR bits are defined below.
Table 13-12. ESR Bit Settings
Field
0–3
4
PIL
5
PPR
6
PTR
7
FP
8
ST
Description
Reserved
Illegal Instruction exception
Privileged Instruction exception
Trap exception
Floating-point operation
Store operation
9
10
DLK
11
ILK
12
AP
13
PUO
14
BO
15
PIE
16–23
Reserved
Data Cache Locking
Instruction Cache Locking
Reserved
Unimplemented Operation exception
Byte Ordering exception
Mismatched Instruction Storage exception
Reserved
Reserved
Associated Interrupt Type
—
Program
Program
Program
Program
Alignment
Data Storage
Data TLB
—
Data Storage
Data Storage
—
Program
Data Storage
Instruction Storage
—
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-21