PXR40RM Datasheet, PDF (965/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
26.4.5.3.11 Receiver Overrun
When the eSCI module has received a frame and attempts to transfer the payload data of the received frame
into the SCI Data Register (ESCI_DR) but neither the application nor the DMA controller has read the SCI
Data Register (ESCI_DR) since its last update, the overrun flag OR in the Interrupt Flag and Status
Register 1 (eSCI_IFSR1) is set. The data contained in SCI Data Register (ESCI_DR) are not changed and
the received data are lost.
26.4.5.3.12 Wake-up Frame Reception
This section describes the reception process when the receiver is in the Wakeup state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into SCI Data Register (ESCI_DR) if the RDRF flag is 0.
If the address-mark wake-up mode is selected and the received frame has the address bit set, the receive
data register full flag RDRF in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive
interrupt enable bit RIE in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF interrupt
request is generated. The RWU bit is cleared, and the receiver enters the Run state via the wake1 transition.
If the idle line wake-up mode is selected and the receiver has detected an idle character, The RWU bit is
cleared, and the receiver enters the Ready state via the wake0 transition.
If any of the receiver errors described in Section 26.4.5.4, Reception Error Reporting, have been occurred,
that corresponding flags will be set.
26.4.5.3.13 Bit Sampling
The receiver samples the selected receiver input (see Section 26.4.5.3.2, Receiver Input Mode Selection)
with the receiver clock RCLK. The sampling for start bit detection is shown in Figure 26-32, the sampling
for data and stop bit reception is shown in Figure 26-33. The samples indicated by dashed arrows are not
used by the receiver. The received data bits are transferred into the internal shift register after the data
strobing. If noise or framing errors were detected, this is flagged as described in Section 26.4.5.4,
Reception Error Reporting.
26.4.5.3.14 Bit Synchronization
To adjust for baud rate mismatch, a synchronization of the cyclic sample counter RSC is performed during
start bit reception as described in Section 26.4.5.3.15, Start Bit Sampling.
Additionally, the synchronization of the cyclic sample counter RSC can be configured to be performed
during data bit reception as described in Section 26.4.5.3.17, Data Bit Synchronization.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-37