PXR40RM Datasheet, PDF (435/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

AMBA Crossbar Switch (XBAR)
• 32-bit address, 64-bit data paths
• Fully concurrent transfers between independent master and slave ports
14.1.4 Modes of Operation
14.1.4.1 Normal Mode
In normal mode, the XBAR provides the register interface and logic that controls crossbar switch
configuration.
14.1.4.2 Debug Mode
The XBAR operation in debug mode is identical to operation in normal mode.
14.2 Memory Map and Register Definition
The memory map for the XBAR program-visible registers is shown in Table 14-2.
Table 14-2. XBAR Register Memory Map
Address
Register
Base = 0xFFF0_4000
XBAR_MPR0—Master priority register for
slave port 0
Base + (0x0004–0x000F) Reserved
Base + 0x0010
XBAR_SGPCR0—General-purpose control
register for slave port 0
Base + (0x0014–0x00FF) Reserved
Base + 0x0100
XBAR_MPR1—Master priority register for
slave port 1
Base +(0x0104–0x010F) Reserved
Base + 0x0110
XBAR_SGPCR1—General-purpose control
register for slave port 1
Base + (0x0114–0x01FF) Reserved
Base + 0x0200
XBAR_MPR2—Master priority register for
slave port 2
Base +(0x0204–0x020F) Reserved
Base + 0x0210
XBAR_SGPCR2—General-purpose control
register for slave port 2
Base + (0x0214–0x05FF) Reserved
Base + 0x0600
XBAR_MPR6—Master priority register for
slave port 6
Base + (0x0604–0x060F) Reserved
Bits Access Reset Value Section/Page
32 R/W 0x7654_3210 14.2.1.1/14-4
32 R/W 0x0000_0000 14.2.1.2/14-6
32 R/W 0x7654_3210 14.2.1.1/14-4
32 R/W 0x0000_0000 14.2.1.2/14-6
32 R/W 0x7654_3210 14.2.1.1/14-4
32 R/W 0x0000_0000 14.2.1.2/14-6
32 R/W 0x7654_3210 14.2.1.1/14-4
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
14-3