PXR40RM Datasheet, PDF (1062/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
• The SSS bit in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is
negated. The SSS bit can be set even if a “1” is written to the SSE bit in Section 27.6.2.5, EQADC
CFIFO Control Registers (EQADC_CFCR), in the same write that the MODEx field is changed to
a value other than disabled.
• The trigger detection hardware is reset. If MODEx is changed from disabled to an edge trigger
mode, a new edge, matching that edge trigger mode, is needed to trigger the command transfers
from the CFIFO.
NOTE
CFIFO fill requests, which generated when CFFF is asserted, are not
automatically halted when MODEx is changed to disabled. CFIFO fill
requests will still be generated until CFFE is cleared in Section 27.6.2.6,
EQADC Interrupt and DMA Control Registers (EQADC_IDCR).
27.7.4.6.2 Single-Scan Mode
In single-scan mode, a single pass through a sequence of command messages in a CQueue is performed.
In single-scan software trigger mode, the CFIFO is triggered by an asserted Single-Scan Status bit (SSS)
in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR). The SSS bit is set by
writing “1” to the Single-Scan Enable bit (SSE) in Section 27.6.2.5, EQADC CFIFO Control Registers
(EQADC_CFCR).
In single-scan edge- or level-trigger mode, the respective triggers are only detected when the SSS bit is
asserted. When the SSS bit is negated, all trigger events for that CFIFO are ignored. Writing a “1” to the
SSE bit can be done during the same write cycle that the CFIFO operation mode is configured.
Only the EQADC can clear the SSS bit. Once SSS is asserted, it remains asserted until the EQADC
completes the CQueue scan, or the CFIFO operation mode (MODEx) in Section 27.6.2.5, EQADC CFIFO
Control Registers (EQADC_CFCR), is changed to disabled. The SSSx bit will be negated while MODEx
is disabled.
Single-Scan Software Trigger
When single-scan software trigger mode is selected, the CFIFO is triggered by an asserted SSS bit. The
SSS bit is asserted by writing “1” to the SSE bit. Writing to SSE while SSS is already asserted will not
have any effect on the state of the SSS bit, nor will it cause a trigger overrun event.
The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using
a not-full on-chip CBuffer. When an asserted EOQ bit is encountered, the EQADC will clear the SSS bit.
Setting the SSS bit is required for the EQADC to start the next scan of the queue.
The Pause bit has no effect in single-scan software trigger mode.
Single-Scan Edge Trigger
When SSS is asserted and an edge triggered mode is selected for a CFIFO, an appropriate edge on the
associated trigger signal causes the CFIFO to become TRIGGERED. For example, if rising-edge trigger
mode is selected, the CFIFO becomes TRIGGERED when a rising edge is sensed on the trigger signal.
27-80
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor