PXR40RM Datasheet, PDF (1127/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
28
DIVR
29
OVF
30
OVR
31
IVR
Decimation Filter
Table 28-5. DECFILT_x_MSR Field Descriptions (continued)
Description
Enhanced Debug Monitor Input Data Read Overrun—The DIVR bit indicates that a received sample in the Filter
Interface Input Register was overwritten by a new sample and was not read by the CPU/DMA. This flag
generates an Interrupt Request if enabled by the ERREN bit in the Configuration Register. This Flag is cleared
by the DIVRC Status bit or by a soft reset of the decimation filter.
0 Input Data Read Overrun did not occur in Enhanced Debug monitor
1 Enhanced Debug Monitor Input Data Read Overrun occurred
Filter Overflow Flag—The OVF bit indicates that an overflow occurred in the filtered sample result. This flag
generates an Interrupt Request if enabled by the ERREN bit in the Configuration Register. This Flag is cleared
by the OVFC Status bit or by a soft reset of the decimation filter.
0 No overflow
1 Overflow occurred
Output Interface Buffer Overrun—The OVR bit indicates that a decimated sample was overwritten by a new
sample in the Interface Output Buffer Register. This flag generates an Interrupt Request if enabled by the
ERREN bit in the Configuration Register. This Flag is cleared by the OVRC Status bit or by a soft reset of the
decimation filter.
0 No Output Overrun
1 Filter Output Overrun occurred
Input Interface Buffer Overrun—The IVR bit indicates that a received sample in the Filter Interface Input Register
was overwritten by a new sample. This flag generates an Interrupt Request if enabled by the ERREN bit in the
Configuration Register. This Flag is cleared by the IVRC Status bit or by a soft reset of the decimation filter.
0 Input Buffer Overrun did not occur
1 Input Buffer Overrun occurred
Note:
28.2.2.3 Decimation Filter Module Extended Configuration Register
(DECFILT_x_MXCR)
Address: DECFILT_x_BASE + 0x008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
00 0
0
0
0
0
0
0
000
SDMAE SSIG SSAT SCSAT
W
SRQ SZRO
Reset 0
00
0
00
0
0
0
0
0
0
0
000
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30
31
R
0
00
0
SISEL
SZROSEL
SHLTSEL
W
SRQSEL
0
0
SENSEL
Reset 0
00
0
00
0
0
0
0
0
0
0
000
Figure 28-4. Decimation Filter Extended Configuration Register (DECFILT_x_MXCR)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-13