PXR40RM Datasheet, PDF (463/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Memory Protection Unit (MPU)
16.1.2 Features
The MPU has these major features:
• Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— MPU is invalid at reset, thus no access restrictions are enforced
— Two types of access control definitions: processor core bus master (e200z7) supports the
traditional {read, write, execute} permissions with independent definitions for supervisor and
user mode accesses; the remaining non-core bus masters (eDMA_A, eDMA_B, FlexRay)
support {read, write} attributes
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter the access rights of a descriptor only
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software
• Support for four AHB slave port connections
— PBRIDGE_A, PBRIDGE_B, EBI (development bus), general purpose SRAM
— MPU hardware monitors every AHB slave port access using the pre-programmed memory
region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit; in the event of an
access error, the AHB reference is terminated with an error response and the MPU inhibits the
bus cycle being sent to the targeted slave device
— 64-bit error registers, one for each AHB slave port, capture the last faulting address, attributes,
and detail information
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
16-3