PXR40RM Datasheet, PDF (201/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
The following table describes the fields in the overrun status register:
Table 7-14. SIU_OSR Bit Field Descriptions
Field
Description
0–15
16–31
OVFn
Reserved
Overrun flag n. This bit is set when an overrun occurs on IRQ[n]. Bit 31 (OVF0) is the overrun flag for IRQ[0]; bit 16
(OVF15) is overrun flag for IRQ[15].
0 No overrun occurred.
1 An overrun occurred.
7.3.1.8 Overrun Request Enable Register (SIU_ORER)
The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If
the overrun request enable bit and the flag bit are set, the single combined overrun request from the SIU
to the interrupt controller is asserted.
Address: SIU_BASE + 0x0024
Access: R/W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R _ORE
W ¹⁵
Reset 0
17
ORE
14
0
18
19
20
21 22 23 24 25 26 27 28 29 30 31
ORE ORE ORE ORE ORE ORE ORE ORE ORE ORE ORE ORE ORE ORE
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-9. Overrun Request Enable Register (SIU_ORER)
The following table describes the fields in the overrun request enable register:
Table 7-15. SIU_ORER Bit Field Descriptions
Field
Function
0–15
16–31
OREn
Reserved
Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0)
is the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15].
0 Overrun request is disabled.
1 Overrun request is enabled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-19