PXR40RM Datasheet, PDF (715/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FLEXRAY
CHI
reg(A)
cfg(A)
reg(B)
cfg(B)
FlexRay Communication Controller (FLEXRAY)
PE
channel A
cCrcInit[A]
channel B
cCrcInit[B]
FR_A_RX
FR_A_TX
FR_A_TX_EN
FlexRay Channel A
FlexRay Bus Driver
Channel A
FR_B_RX
FR_B_TX
FR_B_TX_EN
FLEXRAY
CHI
reg(A)
cfg(A)
reg(B)
cfg(B)
Figure 22-140. Single Channel Device Mode (Channel A)
PE
channel A
cCrcInit[A]
channel B
cCrcInit[B]
FR_A_RX
FR_A_TX
FR_A_TX_EN
FlexRay Bus Driver ^{FlexRay Channel B}
Channel A
Init Value for Frame CRC is cCrcInit[B]
FR_B_RX
FR_B_TX
FR_B_TX_EN
Figure 22-141. Single Channel Device Mode (Channel B)
22.6.11 External Clock Synchronization
The application of the external rate and offset correction is triggered when the application writes to the
EOC_AP and ERC_AP fields in the Protocol Operation Control Register (POCR). The PE applies the
external correction values in the next even-odd cycle pair as shown in Figure 22-142 and Figure 22-143.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-131