PXR40RM Datasheet, PDF (539/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Offset: EDMA_A_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
CXFR ECX
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
R
GRP3PRI
W
Reset 1
1
18
19
GRP2PRI
20
21
GRP1PRI
22
23
24
25
26
27
28
29
30
31
0
GRP0PRI EMLM CLM HALT HOE ERGA ERCA EDBG
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Figure 21-2. eDMA Control Register (EDMA_A_CR)
Offset: EDMA_B_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
CXFR ECX
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R0
W
Reset 0
Field
0–13
14
CXFR
15
ECX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
GRP1
PRI
0
GRP0
PRI
EMLM
CLM
HALT
HOE
ERGA ERCA EDBG
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Figure 21-3. eDMA Control Register (EDMA_B_CR)
Table 21-4. EDMA_A_MCR Field Descriptions
Description
Reserved
Cancel Transfer.
0 Normal operation.
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be finished.
The cancel takes effect after the last write of the current read/write sequence. The CXFR bit clears
itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop
was completed.
Error cancel transfer.
0 Normal operation.
1 Cancel the remaining data transfer in the same fashion as the CXFR cancel transfer. Stop the
executing channel and force the minor loop to be finished. The cancel takes effect after the last write
of the current read/write sequence. The ECX bit clears itself after the cancel has been honored. In
addition to cancelling the transfer, the ECX treats the cancel as an error condition; thus updating the
EDMA_x_ESR register and generating an optional error interrupt. See Section 21.3.2.2, eDMA Error
Status Register (EDMA_x_ESR).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-15