PXR40RM Datasheet, PDF (627/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
OPT
SDVEN
SIDEN
FlexRay Communication Controller (FLEXRAY)
Table 22-39. SFTCCSR Field Descriptions (continued)
Description
One Pair Trigger — This trigger bit controls whether the controller writes continuously or only one pair of
Sync Frame Tables into the flexray memory.
If this trigger is set to 1 while SDVEN or SIDEN is set to 1, the controller writes only one pair of the enabled
Sync Frame Tables corresponding to the next even-odd-cycle pair into the flexray memory. In this case, the
controller clears the SDVEN or SIDEN bits immediately.
If this trigger is set to 0 while SDVEN or SIDEN is set to 1, the controller writes continuously the enabled Sync
Frame Tables into the flexray memory.
0 Write continuously pairs of enabled Sync Frame Tables into flexray memory.
1 Write only one pair of enabled Sync Frame Tables into flexray memory.
Sync Frame Deviation Table Enable — This bit controls the generation of the Sync Frame Deviation Tables.
The application must set this bit to request the controller to write the Sync Frame Deviation Tables into the
flexray memory.
0 Do not write Sync Frame Deviation Tables
1 Write Sync Frame Deviation Tables into flexray memory
Note: If SDVEN is set to 1, then SIDEN must also be set to 1.
Sync Frame ID Table Enable — This bit controls the generation of the Sync Frame ID Tables. The
application must set this bit to 1 to request the controller to write the Sync Frame ID Tables into the flexray
memory.
0 Do not write Sync Frame ID Tables
1 Write Sync Frame ID Tables into flexray memory
22.5.2.34 Sync Frame ID Rejection Filter Register (SFIDRFR)
Base + 0x0046
0
1
R0
0
W
Reset 0
0
16-bit write access required
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
SYNFRID
0
0
0
0
0
0
0
0
0
0
0
Figure 22-34. Sync Frame ID Rejection Filter Register (SFIDRFR)
Write: Normal Mode
13
14
15
0
0
0
This register defines the Sync Frame Rejection Filter ID. The application must update this register outside
of the static segment. If the application updates this register in the static segment, it can appear that the
controller accepts the sync frame in the current cycle.
Table 22-40. SFIDRFR Field Descriptions
Field
SYNFRID
Description
Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for clock
synchronization. For details see Section 22.6.15.2, Sync Frame Rejection Filtering.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-43