PXR40RM Datasheet, PDF (168/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 6-6. ESYNCR2 Bit Field Descriptions (continued)
Field
Description
10
LOCRE
Loss-of-Clock Reset Enable. The LOCRE bit determines how the integration module handles a loss-of-clock
condition when LOCEN is equal to 1. LOCRE has no effect when LOCEN is equal to 0.
If the LOCF bit in the SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an immediate
reset.
The LOCRE bit has no effect in PLL Off mode.
0 Assert reset on loss of clock is disabled.
1 Assert reset on loss of clock.
11
LOLIRQ
Loss-of-Lock Interrupt Request. The LOLIRQ bit determines how the integration module handles a
loss-of-lock indication. See Section 6.6.1, Loss-of-Lock Interrupt Request, for more information.
When operating in normal mode, the PLL must be locked before setting the LOLIRQ bit. Otherwise an
interrupt is immediately requested.
The LOLIRQ bit has no effect in PLL Off mode.
0 Request interrupt is disabled.
1 Request interrupt.
12
LOCIRQ
Loss- of-Clock Interrupt Request. The LOCIRQ bit determines how the integration module handles a loss-
of-clock condition when LOCEN = 1. LOCIRQ has no effect when LOCEN = 0.
If the LOCF bit in the SYNSR indicates a loss-of-clock condition, setting (or having previously set) the
LOCIRQ bit causes an interrupt request.
The LOCIRQ bit has no effect in PLL Off mode.
0 Request interrupt on loss of clock is disabled.
1 Request interrupt on loss of clock.
13
Reserved
14–15
ERATE¹
Enhanced Modulation Rate. The ERATE bits control the rate of frequency modulation applied to the system
frequency. Table 6-7 shows the allowable modulation rates.
16
CLKCFG_DIS
The CLKCFG_DIS bit is used to disable the ability to change the PLL mode using the CLKCFG bits. This
protects the system from errant software writes and/or bit flips on the CLKCFG[2:0] bits that could change
the PLL clock mode.
Note: If the PLL is configured for PLL Off mode when the CLKCFG_DIS bit is set, the PLL will automatically
enter normal mode. For this reason, it is advisable to set the PLL for the desired mode (normal mode
with crystal reference or normal mode with external reference) before setting the CLKCFG_DIS bit to
protect from inadvertent mode changes.
0 Writes to CLKCFG[2:0] enabled.
1 Writes to CLKCFG[2:0] disabled.
17–20
21–23
EDEPTH²
Reserved
Enhanced Modulation Depth. The EDEPTH bit field controls the frequency modulation depth², and in
conjunction with the SYNFMCR[FMDAC_EN] bit enables frequency modulation. The EDEPTH bit must be
set to a non-zero value for FM operation. The sequence for enabling and configuring FM operation is
described in Section 6.4.3.4.2, Programming System Clock Frequency With Frequency Modulation. This
program sequence must be followed exactly to insure proper operation of the FM.
24–25
Reserved
6-10
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor