PXR40RM Datasheet, PDF (1105/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
EQADC FIFO and Interrupt Status Registers (EQADC_FISR).
5. When the EQADC receives a conversion result for RFIFO5, it generates an interrupt request.
RFIFO Pop Register 5 (EQADC_RFPR5) can be popped to read the result. Refer to
Section 27.6.2.4, EQADC Result FIFO Pop Registers (EQADC_RFPR).
27.8.4 Modifying Queues
More CQueues may be needed than the six supported by the EQADC. These additional CQueues can be
supported by interrupting command transfers from a configured CFIFO, even if it is TRIGGERED and
transferring, modifying the corresponding CQueue in the RAM or associating another CQueue to it, and
restarting the CFIFO. More details on disabling a CFIFO are described in Section 27.7.4.6.1, Disabled
Mode.
1. Determine the resumption conditions when later resuming the scan of the CQueue at the point
before it was modified.
a. Change MODEx in Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR), to
Disabled. Refer to Section 27.7.4.6.1, Disabled Mode, for a description of what happens when
MODEx is changed to Disabled.
b. Poll CFSx until it becomes IDLE in Section 27.6.2.10, EQADC CFIFO Status Register
(EQADC_CFSR).
c. Read and save TC_CFx in Section 27.6.2.8, EQADC CFIFO Transfer Counter Registers
(EQADC_CFTCR), for later resuming the scan of the queue. The TC_CFx provides the point
of resumption.
d. Since all result data may not have being stored in the appropriate RFIFO at the time MODEx
is changed to disable, wait for all expected results to be stored in the RFIFO/RQueue before
reconfiguring the DMAC to work with the modified RQueue. The number of results that must
return can be estimated from the TC_CFx value obtained above.
2. Disable the DMAC from responding to the DMA request generated by CFFFx and RFDFx in
Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR).
3. Write “0x0000” to the TC_CFx field.
4. Load the new configuration and conversion commands into RAM. Configure the DMAC to support
the new CQueue/RQueue, but do not configure it yet to respond to DMA requests from
CFIFOx/RFIFOx.
5. If necessary, modify Section 27.6.2.6, EQADC Interrupt and DMA Control Registers
(EQADC_IDCR), to suit the modified CQueue.
6. Write “1” to CFINVx in Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR), to
invalidate the entries of CFIFOx. Perform any other modifications to EQADC_CFCR except
changing MODEx from Disabled.
7. Configure the DMAC to respond to DMA requests generated by CFFFx and RFDFx.
8. Change MODEx to the modified CFIFO operation mode. Write “1” to SSEx to trigger CFIFOx if
MODEx is software trigger.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-123