PXR40RM Datasheet, PDF (1406/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
0
1
2
3
4
R
CENSOR_CTRL
W
Reset: *¹
*
*
*
*
1 _{The reset value of CENSOR_CTRL is 64’b0.}
Figure 1. CENSOR_CTRL Register
CENSOR_CTRL - Censorship Control
The CENSOR_CTRL bits are used to control chip-top censorship functions.
32.3.5 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST, SAMPLE or
SAMPLE/PRELOAD instructions are active. It is used to capture input pin data, force fixed values on
output pins, and select a logic value and direction for bidirectional pins. Each bit of the boundary scan
register represents a separate boundary scan register cell, as described in the IEEE 1149.1-2001 standard
and discussed in Section 32.4.5, Boundary Scan.
32.4 Functional Description
32.4.1 JTAGC Reset Configuration
While in reset, the TAP controller is forced into the test-logic-reset state, thus disabling the test logic and
allowing normal operation of the on-chip system logic. In addition, the instruction register is loaded with
the IDCODE instruction.
32.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port
The JTAGC uses the IEEE 1149.1-2001 TAP for accessing registers. This port can be shared with other
TAP controllers on the MCU. Ownership of the port is determined by the value of the JCOMP signal and
the currently loaded instruction. For more detail on TAP sharing via JTAGC instructions refer to
Section 32.4.4.2, ACCESS_AUX_TAP_x Instructions.
Data is shifted between TDI and TDO though the selected register starting with the least significant bit, as
illustrated in Figure 32-4. This applies for the instruction register, test data registers, and the bypass
register.
MSB
LSB
TDI
Selected register
TDO
Figure 32-4. Shifting Data Through a Register
32.4.3 TAP Controller State Machine
32-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor