PXR40RM Datasheet, PDF (564/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 21-21. TCDn Field Descriptions (continued)
Field
252 /
0x1C [28]
D_REQ
253 /
0x1C [29]
INT_HALF
254 /
0x1C [30]
INT_MAJ
255 /
0x1C [31]
START
Description
Disable hardware request. If this flag is set, the eDMA hardware automatically clears the
corresponding EDMA_A_ERQH or EDMA_x_ERQL bit when the current major iteration count
reaches zero.
0 The channel’s EDMA_A_ERQH or EDMA_x_ERQL bit is not affected.
1 The channel’s EDMA_A_ERQH or EDMA_x_ERQL bit is cleared when the outer major
loop is complete.
Enable an interrupt when major counter is half complete. If this flag is set, the channel
generates an interrupt request by setting the appropriate bit in the EDMA_A_ERQH or
EDMA_x_ERQL when the current major iteration count reaches the halfway point.
Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This
halfway point interrupt request is provided to support double-buffered (aka ping-pong)
schemes, or other types of data movement where the processor needs an early indication of
the transfer’s progress. CITER = BITER = 1 with INT_HALF enabled will generate an interrupt
as it satisfies the equation (CITER == (BITER >> 1)) after a single activation.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
Enable an interrupt when major iteration count completes. If this flag is set, the channel
generates an interrupt request by setting the appropriate bit in the EDMA_A_ERQH or
EDMA_x_ERQL when the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
Channel start. If this flag is set the channel is requesting service. The eDMA hardware
automatically clears this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
21.4 Functional Description
This section provides an overview of the microarchitecture and functional operation of the eDMA block.
The eDMA module is partitioned into two major modules: the DMA engine and the transfer control
descriptor local memory. The DMA engine is further partitioned into four submodules, which are detailed
below.
• DMA engine
— Address path: This module implements registered versions of two channel transfer control
descriptors: channel x and channel y, and is responsible for all the master bus address
calculations. All the implemented channels provide the same functionality. This hardware
structure allows the data transfers associated with one channel to be preempted after the
completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. After a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by EDMA_x_CPRn[ECP]) where a large data move operation
can be preempted to minimize the time another channel is blocked from execution.
— When another channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other address path channel{x,y}. After
the inner minor loop completes execution, the address path hardware writes the new values for
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PXR40 Microcontroller Reference Manual, Rev. 1
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