PXR40RM Datasheet, PDF (484/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Error Correction Status Module (ECSM)
Table 17-4. ECSM_ECR Field Descriptions (continued)
Field
Description
6
ERNCR
Enable RAM Non-Correctable Reporting. The occurrence of a non-correctable multi-bit RAM error generates an
ECSM ECC interrupt request as signaled by the assertion of ECSM_ESR[RNCE]. The faulting address, attributes,
and data in either the 512 KB or 80 KB array are also captured in the ECSM_REAR, ECSM_RESR, ECSM_REMR,
ECSM_REAT, and ECSM_REDR registers.
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
7
EFNCR
Enable Flash Non-Correctable Reporting. The occurrence of a non-correctable multi-bit flash error generates an
ECSM ECC interrupt request as signaled by the assertion of ECSM_ESR[FNCE]. The faulting address, attributes,
and data are also captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers.
0 Reporting of non-correctable flash errors is disabled.
1 Reporting of non-correctable flash errors is enabled.
17.2.2.6 ECC Status Register (ECSM_ESR)
The ECC status register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ECSM_ESR signals the last properly-enabled memory event to be
detected. An ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is
asserted.
The ECSM allows a maximum of one bit of the ECSM_ESR to be asserted at any given time. This
preserves the association between the ECSM_ESR and the corresponding address and attribute registers,
which are loaded on each occurrence of an properly-enabled ECC event. If there is a pending ECC
interrupt and another properly-enabled ECC event occurs, the ECSM hardware automatically handles the
ECSM_ESR reporting, clearing the previous data and loading the new state and thus guaranteeing that
only a single flag is asserted.
To maintain the coherent software view of the reported event, the following sequence in the ECSM error
interrupt service routine is suggested:
1. Read the ECSM_ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two
values are different, repeat from step one.
4. When the values are identical, write a 1 to the asserted ECSM_ESR flag to negate the interrupt
request.
See Figure 17-3 and Table 17-5 for the ECC status register definition.
Offset: ECSM_BASE_ADDR + 0x0047
0
1
2
3
4
5
R
0
0
R1BC
F1BC
0
0
W
w1c
w1c
Reset
0
0
0
0
0
0
Figure 17-3. ECC Status (ECSM_ESR) Register
Access: User read/write
6
RNCE
w1c
0
7
FNCE
w1c
0
17-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor