PXR40RM Datasheet, PDF (753/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
The control register gathers bits reflecting the status of the unified channel input/output signals and the
overflow condition of the internal counter, as well as several read/write control bits.
Table 23-8. EMIOS_CCR[n] Field Descriptions
Field
0
FREN
1
ODIS
2–3
ODISSL
Description
Freeze Enable Bit. The FREN bit, if set and validated by FRZ bit in EMIOS_MCR register, freezes all registers’
values when in debug mode, allowing the MCU to perform debug functions.
0 Normal operation.
1 Freeze unified channel registers’ values.
Output Disable Bit. The ODIS bit allows disabling the output pin when running any of the output modes with
the exception of GPIO mode.
0 The output pin operates normally.
1 If the selected output disable input signal is asserted, the output pin goes to EDPOL for OPWFMB and
OPWMB modes and to the complement of EDPOL for other modes, but the unified channel continues to
operate normally, i.e., it continues to produce FLAG and matches. When the selected output disable input
signal is negated, the output pin operates normally.
Output Disable Select Bits. The ODISSL bits select an eMIOS channel flag to disable an output when the flag
asserts.
ODISSL
00
01
10
11
eMIOS Channel Flag Number
11
10
9
8
4–5
UCPRE
Prescaler Bits. The UCPRE bits select the clock divider value for the internal prescaler of unified channel.
UCPRE
00
01
10
11
Divide Ratio
1
2
3
4
6
UCPREN
7
DMA
8
Prescaler Enable Bit. The UCPREN bit enables the prescaler counter.
0 Prescaler disabled.
1 Prescaler enabled and the prescaler counter is loaded with UCCPRE value.
Direct Memory Access Bit. The DMA bit selects whether the FLAG generation is used as an interrupt or as a
DMA request.
0 FLAG/overrun assigned to interrupt request.
1 FLAG/overrun assigned to DMA request.
Reserved
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-13