PXR40RM Datasheet, PDF (625/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
22.5.2.31 Sync Frame Counter Register (SFCNTR)
Base + 0x0040
Additional Reset: RUN Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SFEVB
SFEVA
SFODB
SFODA
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-31. Sync Frame Counter Register (SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the controller will not
update the fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the controller will not update
the values SFODB and SFODA.
Table 22-37. SFCNTR Field Descriptions
Field
SFEVB
SFEVB
SFODB
SFODA
Description
Sync Frames Channel B, even cycle — protocol related variable: size of (vsSyncIdListB for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel A, even cycle — protocol related variable: size of (vsSyncIdListA for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel B, odd cycle — protocol related variable: size of (vsSyncIdListB for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Sync Frames Channel A, odd cycle — protocol related variable: size of (vsSyncIdListA for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
22.5.2.32 Sync Frame Table Offset Register (SFTOR)
Base + 0x0042
0
1
R
W
Reset 0
0
2
3
4
5
6
7
8
9
10
11
12
SFT_OFFSET[15:1]
0
0
0
0
0
0
0
0
0
0
0
Figure 22-32. Sync Frame Table Offset Register (SFTOR)
Write: POC:config
13
14
15
0
0
0
0
This register defines the Flexray Memory related offset for sync frame tables. For more details, see
Section 22.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-41