PXR40RM Datasheet, PDF (763/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
The MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
When changing the MODE bits, the application software must go to GPIO mode first to reset the unified
channel’s internal functions properly. Failure to do this could lead to invalid and unexpected output
compare or input capture results or the FLAGs being set incorrectly.
In GPIO input mode (MODE = 000_0000), the FLAG generation is determined according to EDPOL and
EDSEL bits and the input pin status can be determined by reading the UCIN bit.
In GPIO output mode (MODE = 000_0001), the unified channel is used as a single output port pin and the
value of the EDPOL bit is permanently transferred to the output flip-flop.
23.4.1.1.2 Single Action Input Capture (SAIC) Mode
In SAIC mode (MODE = 000_0010), when a triggering event occurs on the input pin, the value on the
selected time base is captured into register A2. At the same time, the FLAG bit is set to indicate that an
input capture has occurred. The EMIOS_CADR[n] register returns the value of register A2. The channel
is ready to capture events as soon as SAIC mode is entered coming out from GPIO mode. The events are
captured as soon as they occur, thus reading register A (EMIOS_CADR) always returns the value of the
latest captured event. Subsequent captures are enabled with no need of further reads from the
EMIOS_CADR[n] register. The FLAG bit is set at any time a new event is captured.
The input capture is triggered by a rising, falling, or either edge on the input pin, as configured by the
EDPOL and EDSEL bits in EMIOS_CCR[n] register.
Figure 23-13 and Figure 23-14 show how the unified channel can be used for input capture.
EDSEL = 1
EDPOL = x
Edge Detect
Edge Detect
Edge Detect
Input Signal¹
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
FLAG Pin/Register
A2 (Captured) Value^{2 0xxxxxxx}
0x001000
0x001250
0x0016A0
Notes:
1. After input filter
2. EMIOS_CADR[n]  A2
Figure 23-13. SAIC with Rising Edge Triggering Example
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-23