PXR40RM Datasheet, PDF (771/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[6] = 1
EDSEL = 1
EDPOL = x
Write to A2
Write to A2
Write to A2
Write to B2
Write to B2
Write toB2
Output Flip-Flop
Selected Counter Bus
0x000000 0x000001 0x000002 0x000000 0x000001 0x000002 0x000000 0x000001 0x000002
System Clock
Enabled A1 Match
Enabled B1 Match
FLAG Set Event
FLAG Pin/Register
FLAG Clear
OU¹
A1 Value² 0xxxxxxx 0x000001
A2 Value³ 0xxxxxxx 0x000001
B1 Value⁴ 0xxxxxxx 0x000002
B2 Value⁵ 0xxxxxxx 0x000002
0x000001
0x000002
0x000001 0x000001
0x000001
0x000002
0x000002
0x000002
Note: 1. OU[n] bit of EMIOS_OUDR register
2. EMIOS_CADR[n] = A1 (when reading)
3. EMIOS_CADR[n] = A2 (when writing)
4. EMIOS_CBDR[n] = B1 (when reading)
5. EMIOS_CBDR[n] = B2 (when writing)
Figure 23-24. DAOC with Transfer Disabling Example
23.4.1.1.7 Pulse/Edge Accumulation (PEA) Mode
The PEA mode returns the time taken to detect a desired number of input events. The MODE[6] bit selects
between continuous or single-shot operation.
After writing to register A1, the internal counter is cleared on the first input event, ready to start counting
input events, and the selected timebase is latched into register B2. On the match between the internal
counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held
in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.
The desired time interval can be determined by subtracting register B1 from A2. Registers
EMIOS_CADR[n] and EMIOS_CBDR[n] return the values in register A2 and B1, respectively.
As part of the coherency mechanism, reading EMIOS_CADR[n] disables transfers from B2 to B1. These
transfers are disabled until the next read of the EMIOS_CBDR[n] register. Reading the EMIOS_CBDR[n]
register re-enables transfers from B2 to B1, to take effect at the next transfer event, as previously
described.¹
1. If B1 was not updated due to B2 to B1 transfer being disabled after reading register EMIOS_CADR[n], further
EMIOS_CADR[n] and EMIOS_CBDR[n] reads will not return coherent data until a new bus capture is triggered to registers A2
and B2. This capture event is indicated by the channel FLAG being asserted. If enabled, the FLAG also generates an interrupt.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-31