PXR40RM Datasheet, PDF (123/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Resets
pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH
input pins. Figure 4-1 and Figure 4-2 show logic flows of the reset state machine on assertion of RESET.
4.3.2 RSTOUT
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven
to the low state by the MCU for all internal and external reset sources.
If the PLL is configured for normal mode, the RSTOUT pin is asserted for 2400 clock cycles, plus 4 cycles
for sampling of the configuration pins. See Table 4-3 for other source values.
The RSTOUT pin can also be asserted by a write to the SER bit of the System Reset Control Register
(SIU_SRCR); however no system reset occurs under this circumstance.
Table 4-3. Clock Cycles for Different Reset Sources
Source
Description
Number of clock cycles Number of clock cycles
(short count)¹
(long count)²
SIU_POR
Power On Reset
SIU_ER
External Reset (RESET pin)
SIU_LLR
Loss of Lock Reset
SIU_WTR
Watchdog Timer Reset
SIU_CR
Core Reset
SIU_SWTR
Software Watchdog Timer Reset
SIU_LCR
Loss of Clock Reset
SIU_SSR
Software System Reset
SIU_SER
Software External Reset
1 _{Used in the XOSC and XREF modes.}
2 _{Used in the bypass and 1:1 modes.}
2400
2410
2420
2430
2440
2450
2460
2470
2480
16000
16100
16200
16300
16400
16500
16600
16700
16800
4.4 FMPLL Lock Gating Signal
The FMPLL Loss of Lock reset request is connected to both a reset request and a reset gating signal in the
SIU. The FMPLL asserts the Loss of Lock reset request until the PLL has achieved lock.
4.5 Reset Source Descriptions
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-1 and Figure 4-2.
Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing
of reset for all reset sources.
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-3