PXR40RM Datasheet, PDF (462/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Memory Protection Unit (MPU)
16.1.1 Block Diagram
A simplified block diagram illustrates how the MPU block is connected to the four XBAR MPU ports and
the shared port splitter (see Figure 16-1 and Table 16-1).
e200z7
e200z7,
Nexus 3
eDMA_A
eDMA_B
FlexRay
XBAR
ports
Masters Slaves
On-chip Flash
EBI
On-chip SRAM
PBRIDGE_A
PBRDIGE_B
MPU0 MPU1 MPU2 MPU3
MPU Port Numbers
Figure 16-1. MPU Connections to XBAR Slaves
Table 16-1 enumerates the MPU Ports that are attached to slave modules. The Master IDs of all bus master
modules are also shown, as their values are required to configure certain MPU registers described in this
chapter.
Table 16-1. XBAR Switch Ports
Module
e200z7 core—CPU instruction
e200z7—Data
Nexus 3
eDMA_A
eDMA_B
FlexRay
On-chip Flash
EBI (development bus)
On-chip SRAM
Peripheral bridge A (PBRIDGE_A)
Peripheral bridge B (PBRIDGE_B)
MPU Master
ID
0
0
0
4
5
6
—
—
—
—
—
MPU Slave
Port
—
—
—
—
—
—
—
0
1
2
3
16-2
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor